Also, CT loop filters offer inherent anti-aliasing and thus save the need for explicit anti-aliasing filter before the ADC. The CT operation of the loop filter relaxes the requirements on the gain-bandwidth product (GBW) of the adopted amplifiers and hence allows the operation at higher speeds or lower power consumption compared to discrete-time (DT) implementations. This qualifies ΔƩ ADCs to benefit from increasing speeds of operation offered by advanced deep submicron CMOS technologies (maximum cutoff-frequency f T > 300 GHzin 45nm ) to meet higher resolution requirements for modern and future wireless services at minimum power overhead.Ĭontinuous-time (CT) ΔƩ ADCs are widely used in wideband low power wireless receivers. Specifically, for a given ΔƩ modulator and channel bandwidth (BW), higher effective number of bits (ENOB) can be achieved by increasing the oversampling ratio (OSR).
Second, ΔƩ modulators use oversampling and hence trade speed for resolution. Thus, the simplified analog part (ΔƩ modulator) and the digital filtering can be efficiently reconfigured to fulfill performance requirements of different standards at minimum power consumption. Particularly, ΔƩ ADC implementations span analog and digital domains (ΔƩ pulse density modulation + digital decimation and filtering, as shown in Figure 2) and hence exploit DSP to relax hardware requirements on analog blocks. First, they trade DSP for relaxed analog circuit complexity. This means that the main limitation on increasing the ADC performance in terms of SNR and speed is the specification on the clock-jitter of 0.1ps.ĭelta-sigma (ΔƩ) ADCs are the convenient choice in low power and state-of-the-art multi-standard wireless receivers for two main reasons. As can be seen from the chart, the performance of most ADCs falls below the line corresponding to 1ps rms jitter, few ADCs reside in the range between 1ps and 0.1ps, and almost all ADC implementations reported so far are beyond the 0.1ps rms jitter line. The straight lines show the limitation on the achievable signal-to-noise ratio (SNR) by clock-jitter for jitter root-mean square (rms) values of 1ps and 0.1ps. Figure 1 shows a survey chart of the analog-to-digital converter (ADC) implementations reported in IEEE International solid-state circuits conference (ISSCC) and VLSI Symposium since 1997. phase-locked loop, PLL) add to the clock waveform and cause uncertainty in the timing of the zero-crossing instants from cycle to cycle. Particularly, noise components induced by several noise sources in the system providing the clock (e.g. Clock-jitter is a common problem associated with clock generators due to uncertainty in the timing of the clock edges caused by the finite phase-noise (PN) in the generated clock waveform. While modern integrated circuits (IC) technologies provide high cut-off frequencies ( f T) for transistors and hence allow the operation at higher speeds, the main limitation against increasing speed of operation of data-converters is the problem of clock-jitter.
20kHz and 40 kHz).The quest for higher data rates in state-of-the-art wireless standards and services calls for wideband and high-resolution data-converters in wireless transceivers.
It implies that, if the frequency of a clock generator is a multiple of another one, they are guaranteed to stay in phase (e.g.
Synchronization: in a multi-device configuration, all clock generators are intrinsically synchronized.Variable frequency: the clock generators support glitch-less reconfiguration during execution as explained in Variable frequency operation with the B-Box/B-Board (PN121).In a multi-device configuration, the clocks are propagated to all the devices and stay synchronized within ☒ ns.
The B-Box RCP and B-Board PRO digital controllers hold 4 clock generators, which provide time-bases to use with various peripherals such as the ADCs, the PWMs, and the control task routine.